JPH0361337B2 - - Google Patents

Info

Publication number
JPH0361337B2
JPH0361337B2 JP57136430A JP13643082A JPH0361337B2 JP H0361337 B2 JPH0361337 B2 JP H0361337B2 JP 57136430 A JP57136430 A JP 57136430A JP 13643082 A JP13643082 A JP 13643082A JP H0361337 B2 JPH0361337 B2 JP H0361337B2
Authority
JP
Japan
Prior art keywords
region
mask layer
area
base
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57136430A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5837961A (ja
Inventor
Burosufueruto Rotaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of JPS5837961A publication Critical patent/JPS5837961A/ja
Publication of JPH0361337B2 publication Critical patent/JPH0361337B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/421—Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/919—Compensation doping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/98—Utilizing process equivalents or options

Landscapes

  • Bipolar Transistors (AREA)
JP57136430A 1981-08-08 1982-08-06 少なくとも１個のバイポ−ラプレ−ナトランジスタを備えたモノリシツク集積回路の製造方法 Granted JPS5837961A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP81106214.0 1981-08-08
EP81106214A EP0071665B1 (de) 1981-08-08 1981-08-08 Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor

Publications (2)

Publication Number Publication Date
JPS5837961A JPS5837961A (ja) 1983-03-05
JPH0361337B2 true JPH0361337B2 (en]) 1991-09-19

Family

ID=8187852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57136430A Granted JPS5837961A (ja) 1981-08-08 1982-08-06 少なくとも１個のバイポ−ラプレ−ナトランジスタを備えたモノリシツク集積回路の製造方法

Country Status (4)

Country Link
US (1) US4477965A (en])
EP (1) EP0071665B1 (en])
JP (1) JPS5837961A (en])
DE (1) DE3174397D1 (en])

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
US4567644A (en) * 1982-12-20 1986-02-04 Signetics Corporation Method of making triple diffused ISL structure
EP0116654B1 (de) * 1983-02-12 1986-12-10 Deutsche ITT Industries GmbH Verfahren zum Herstellen von bipolaren Planartransistoren
EP0122313B1 (de) * 1983-04-18 1987-01-07 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem integrierten Isolierschicht-Feldeffekttransistor
DE3317437A1 (de) * 1983-05-13 1984-11-15 Deutsche Itt Industries Gmbh, 7800 Freiburg Planartransistor mit niedrigem rauschfaktor und verfahren zu dessen herstellung
US4584763A (en) * 1983-12-15 1986-04-29 International Business Machines Corporation One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation
JPS60258964A (ja) * 1984-06-06 1985-12-20 Hitachi Ltd 半導体装置の製造方法
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
DE3571366D1 (en) * 1985-09-21 1989-08-10 Itt Ind Gmbh Deutsche Method of applying a contact to a contact area for a semiconductor substrate
US4753834A (en) * 1985-10-07 1988-06-28 Kimberly-Clark Corporation Nonwoven web with improved softness
EP0239652B1 (de) * 1986-03-22 1991-07-24 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor
US4721685A (en) * 1986-04-18 1988-01-26 Sperry Corporation Single layer poly fabrication method and device with shallow emitter/base junctions and optimized channel stopper
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
DE3683054D1 (de) * 1986-12-12 1992-01-30 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung mit mindestens einem bipolaren planartransistor.
EP0271599B1 (de) * 1986-12-18 1991-09-04 Deutsche ITT Industries GmbH Kollektorkontakt eines integrierten Bipolartransistors
US4740478A (en) * 1987-01-30 1988-04-26 Motorola Inc. Integrated circuit method using double implant doping
US4784966A (en) * 1987-06-02 1988-11-15 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US5005066A (en) * 1987-06-02 1991-04-02 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
KR890005885A (ko) * 1987-09-26 1989-05-17 강진구 바이폴라 트랜지스터의 제조방법
US5238849A (en) * 1990-08-30 1993-08-24 Nec Corporation Method of fabricating semiconductor device
DE19540309A1 (de) * 1995-10-28 1997-04-30 Philips Patentverwaltung Halbleiterbauelement mit Passivierungsaufbau
DE19611692C2 (de) * 1996-03-25 2002-07-18 Infineon Technologies Ag Bipolartransistor mit Hochenergie-implantiertem Kollektor und Herstellverfahren
USD414405S (en) 1997-11-24 1999-09-28 Tompkins Jeffrey D Cylindrical holder

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE405526B (sv) * 1973-07-16 1978-12-11 Western Electric Co Transistor och sett for dess tillverkning
JPS5167069A (en) * 1974-12-07 1976-06-10 Fujitsu Ltd Handotaisochino seizohoho
JPS5278387A (en) * 1975-12-24 1977-07-01 Fujitsu Ltd Production of semiconductor device
JPS5952550B2 (ja) * 1976-12-27 1984-12-20 富士通株式会社 半導体装置の製造方法
US4111720A (en) * 1977-03-31 1978-09-05 International Business Machines Corporation Method for forming a non-epitaxial bipolar integrated circuit
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
JPS5852339B2 (ja) * 1979-03-20 1983-11-22 富士通株式会社 半導体装置の製造方法
US4376664A (en) * 1979-05-31 1983-03-15 Fujitsu Limited Method of producing a semiconductor device
US4242791A (en) * 1979-09-21 1981-01-06 International Business Machines Corporation High performance bipolar transistors fabricated by post emitter base implantation process

Also Published As

Publication number Publication date
EP0071665A1 (de) 1983-02-16
DE3174397D1 (en) 1986-05-22
EP0071665B1 (de) 1986-04-16
US4477965A (en) 1984-10-23
JPS5837961A (ja) 1983-03-05

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